Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. The desire for higher performance circuits has driven the development of high-speed sub-100 nanometer (nm) silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. In SOI technology, metal-oxide semiconductor field-effect transistors (MOSFETs) are formed on a thin layer of silicon overlying a layer of insulating material such as silicon oxide. Devices formed on SOI offer many advantages over their bulk counterparts. For example, SOI devices generally have a reduced junction capacitance, little to no reverse body effect, soft-error immunity, full dielectric isolation, and little to no latch-up. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption, among other things, as compared to conventional transistors that are formed on a semiconductor bulk material (e.g., silicon) and not over a layer of insulating material.
One type of SOI device is a fully-depleted (FD-SOI) device. In a FD-SOI device the thin layer of silicon has a thickness that is less than the maximum depletion layer width in the silicon during device operation. Consequently, during operation, the FD-SOI experiences a “full” depletion thereof. FD-SOI devices have an additional advantage over traditional or bulk transistors in that they can be scaled to shorter gate lengths and do not suffer from body effects due to the fact that the body is fully-depleted during device operation. FD-SOI devices are also believed to provide lower off-state leakage currents, higher speeds, fewer soft errors, lower operating voltages and lower gate delay than regular non-SOI transistors.
However, since FD-SOI devices are formed on a thin layer of silicon overlying a layer of insulating material, they can be said to lack a “body tie”, or rather a connection to the underlying semiconductor substrate. This makes it very difficult to produce different types of transistors on the same chip and/or the same or similar types of transistors that have different operating characteristics from being produced on the same chip. For example, multiple transistors having different threshold voltages (Vt's) and/or operating speeds would be difficult to be produced at the same time. Likewise, it would be difficult to produce high voltage I/O transistors while low voltage I/O transistors are also produced. Bulk transistors, on the other hand, do allow such different transistors to be made at the same time. More particularly, since these more traditional transistors are formed on bulk semiconductor material (e.g., silicon) that does not overlie a layer of insulating material, they can be said to have a “body tie”. Essentially, the thicker substrate that the transistors are formed on can accommodate different types of processing, such as different doping concentrations, for example, that enable different devices to be formed on the same chip.
Consequently, it would be desirable to be able to reliably form both FD-SOI and bulk transistors in a single fabrication process so that either of the devices can be employed based on circuit application requirements.